1. Field of the Invention
An object of the present invention is a device for the structural testing of an integrated circuit. It can be applied in the field of semiconductors and, more particularly, in the field of memory cards, called chip cards, provided with electronic integrated circuits to fulfill various functions such as identification, electronic keying functions, storage of information, including information on bank balances etc. An object of the invention is to improve the design of these circuits in order to increase the density of the electronic functions integrated into the same circuit.
2. Description of the Prior Art
Advances in integrated circuit technology are making it possible to design increasingly complex and low-cost circuits. These two factors, complexity and cost, are resulting in an increase in the cost of testing the manufactured circuits. Thus, it is worthwhile to add internal testing circuits. These testing circuits reduce the testing time and, therefore, the overall cost of the total integrated circuit. The addition of internal testing circuits of this type nevertheless, increases the area of the total circuit. Consequently, the area for these testing circuits should be relatively small so that the reduction in the cost of testing is not wiped out by the increase in the cost of manufacturing the circuit. For, the cost of manufacturing a circuit is essentially related to the size of this circuit: the bigger the circuit, the smaller the number of circuits which can be manufactured at the same time; the more advanced, the costlier, the machines will be to manufacture them.
The cost of testing is related chiefly to the testing time. In order to reduce this testing time, structural tests are performed. Structural tests do not correspond to a check on the overall function of an integrated circuit, but rather to a check on the function of internal logic blocks, each logic block being tested separately.
A logic block can be defined as a circuit with inputs and outputs. In response to signals applied to its inputs, it has to deliver expected output signals. The structural test therefore includes introducing input signals of this type, and checking the form of the output signals delivered. Logic blocks are not necessarily organized in such a way as to end, through their inputs and/or outputs, in connection terminals of the total integrated circuit. For, during the normal operation of this total integrated circuit, the signals delivered by these logic blocks, which are then activated by integrated circuit managing signals, do not need to be extracted in most cases. Hence, if a structural test enables a considerable reduction in testing time, and also an exhaustive checking of the behavior of the circuit in all possible situations, it still requires an external reading of all the outputs of all the logic blocks to be tested. This may result in considerable loss of space, and in a corresponding complexity of the total integrated circuit. Ultimately, the gain in testing speed may be counter-balanced by a loss of space, and a smaller capacity of the manufactured circuit.
In practice, this difficulty can be resolved partially by using, a shift register in series which enables the recording, of the signals given by the parallel outputs of a logic block to be tested in series. Thus, the number of connections to be made in the circuit is reduced by the ratio of this parallel/series conversion. However, the shift register itself occupies a great deal of space, especially if the number of bits, namely the number of pulse signals, is great.
In the invention, these drawbacks are overcome by noting that some of the electronic integrated circuits to be tested have memories. To provide access to the memory cells of these memories, these circuits have decoders. The idea of the invention lies in the use of these already existing decoders to control the distribution of the input and/or output signals of the logic blocks to be tested. In the invention, gate circuits, mounted in cascade with the logic blocks and controlled by outputs of the decoder, are simply interposed between the memory and these decoders. In organizing a particular address decoding, it is possible to validate the operation of these gate circuits in such a way that all the functions of a logic block are tested successively or at least in such a way that the signals resulting from the performance of the functions of this logic block are taken into account successively. In one improvement, even the output circuit of the memory is used as an organ for the transmission of test signals by interposing, in series, with the output circuit of the memory, a circuit to neutralize the normal functions of this memory and a circuit to activate the transmission of the signals resulting from the execution of the logic functions.